Forward error correction and framing protocol

ABSTRACT

A serializer and deserializer are disclosed that provide an efficient scheme for both forward error correction and symbol alignment and frame alignment by the deserializer. In particular, the illustrative embodiment provides an efficient method for generating row and column parity bits for an S by K-bit matrix that can, in some cases, require fewer that S+K parity bits. This is particularly useful for when a single word is broken up and its pieces are sent via different serial communications channels and the deserializer needs to be capable of properly reassembling the fragments into the word.

FIELD OF THE INVENTION

[0001] The present invention relates to telecommunications in general,and, more particularly, to an apparatus for converting one or moreparallel words into one or more serialized streams of bits and backagain into parallel words.

BACKGROUND OF THE INVENTION

[0002] There are situations where parallel words of data need to betransmitted via a serial communications channel. In these situations, afirst apparatus converts the words into a serialized stream of bits fortransmission on the serial communications channel. Typically the firstapparatus is known as a serializer.

[0003] At the receiving end of the serial communications channel, asecond apparatus captures the serialized stream of bits and restores itback into parallel words. Typically, the second apparatus is known as adeserializer. Regardless of what the first apparatus and the secondapparatus are called, the second apparatus performs the inverseoperation of the first apparatus.

[0004]FIG. 1 depicts a block diagram of serial communications system 100in the prior art, which comprises: serializer 101, deserializer 102,timing source 103, timing source 104, and serial communications channel111, interconnected as shown.

[0005] Serializer 101 receives a parallel word of bits and a timingsignal (e.g., a clock signal, etc.) from timing source 103 and convertsthe parallel word into a serialized stream of bits for transmission viaserial communications channel 111. For example, serializer 101 cancomprise a parallel-load-in/serial-shift-out register that loads wordsin at a slower rate than it shifts bits out.

[0006] Serial communications channel 111 is a logical channel that canbe carried alone on a physical channel or can be multiplexed with otherlogical channels on a physical channel (e.g., a metal wireline, anoptical fiber, or a wireless channel, etc.).

[0007] Deserializer 102 receives the serialized stream of bits fromserial communications channel 111 and a clock signal from timing source104, captures the serialized stream of bits, and converts it back into aparallel word. For example, deserializer 102 can comprise aserial-shift-in/parallel-unload-out shift register.

[0008] The design and operation of serializer 101 and deserializer 102can be problematic. For example, if a bit error occurs during thetransmission of the serialized stream of bits, the error might not bedetected or corrected by the deserializer. Furthermore, if the word isbroken up and its pieces are sent via different serial communicationschannels, the deserializer can fail to properly reassemble the fragmentsback into a word.

[0009] Therefore, the need exists for a serializer and a deserializerthat are capable of detecting and/or correcting one or more bit errorsthat occur during the transmission of the serialized stream of bits.Furthermore, the need exists for a serializer and a deserializer thatare capable of breaking up a word into pieces for transmission viadifferent serial communications channels of properly reassembling thefragments back into a word.

SUMMARY OF THE INVENTION

[0010] Some embodiments of the present invention enable theserialization of words without some of the costs and disadvantages fordoing so in the prior art. For example, the illustrative embodimentprovides an efficient scheme for forward error correction (i.e., thecorrection of bit errors by the receiver without the retransmission ofthe data by the transmitter). In particular, the illustrative embodimentprovides an efficient method for generating row and column parity bitsfor an S by K-bit matrix that can, in some cases, require fewer that S+Kparity bits.

[0011] Furthermore, the illustrative embodiment provides both symbolalignment and frame alignment by the deserializer in an efficientmanner. This is particularly useful for when a single word is broken upand its pieces are sent via different serial communications channels andthe deserializer needs to be capable of properly reassembling thefragments into the word.

[0012] The illustrative embodiment comprises: receiving a matrix C ofbits, wherein the matrix C has dimensions of S by K and wherein both Sand K are positive integers; generating a plurality of row parity bitsthat are indicative of the parity of a row of bits in a matrix D thathas dimensions of S/y by yK, wherein S/y and yK are positive integers,wherein y is a positive integer other than one, and wherein matrix D isbased on a shuffling function of matrix C; and transmitting the matrix Cof bits and the plurality of row parity bits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 depicts a block diagram of serial communications system 100in the prior art.

[0014]FIG. 2 depicts a block diagram of the first variation of theillustrative embodiment of the present invention.

[0015]FIG. 3 depicts a block diagram of the second variation of theillustrative embodiment of the present invention.

[0016]FIG. 4 depicts a block diagram of the salient components ofmultichannel serializer 201, as depicted in FIGS. 2 and 3.

[0017]FIG. 5 depicts a block diagram of the salient components ofencoder/framer 402-i, as depicted in FIG. 4.

[0018]FIG. 6 depicts a block diagram of the salient components ofmultichannel deserializer 202.

[0019]FIG. 7 depicts a block diagram of the salient components ofdecoder/deframer 603-i.

[0020]FIG. 8 depicts a block diagram of the salient components offorward error corrector 705.

DETAILED DESCRIPTION

[0021]FIG. 2 depicts a block diagram of the first variation of theillustrative embodiment of the present invention, which comprises:multichannel serializer 201, multichannel deserializer 202, N serialcommunications channels 211-1 through 211-N, wherein N is a positiveinteger greater than zero, timing source 203, and timing source 204, allof which are interconnected as shown. In accordance with the firstvariation of the illustrative embodiment of the present invention,multichannel serializer 201 and multichannel deserializer 202 are eachprovided with clock signals that are independent of, and asynchronousto, each other.

[0022]FIG. 3 depicts a block diagram of the second variation of theillustrative embodiment of the present invention, which comprises:multichannel serializer 201, multichannel deserializer 202, N serialcommunications channels 211-1 through 211-N, wherein N is a positiveinteger greater than zero, and timing source 303, all of which areinterconnected as shown. In accordance with the second variation of theillustrative embodiment of the present invention, multichannelserializer 201 and multichannel deserializer 202 are each provided witha clock signal from the same timing source.

[0023] In yet a third variation of the illustrative embodiment, which isnot depicted in the Figures, multichannel deserializer 202 derives thetiming signal at which to deserialize the bit stream from one or more ofthe serialized bit streams themselves. In this variation, theillustrative embodiment can use one or more synchronized oscillators(e.g., phase-locked loops, etc.) to derive the timing signal at which todeserialize the bit stream. In all other respects that are germane tothe present invention, the three variations of the illustrativeembodiment are identical, and, therefore, will be described as one.

[0024] With reference to both FIGS. 2 and 3, there are 64 serialcommunications channels between multichannel serializer 201 andmultichannel deserializer 202 (i.e., N=64). In accordance with theillustrative embodiment, each of serial communications channels 211-1through 211-N is a distinct physical channel and is carried by adistinct optical fiber. In some alternative embodiments of the presentinvention, each of serial communications channels 211-1 through 211-N isa logical channel, and, therefore, some of them are multiplexed andtransmitted to multichannel deserializer 202 via a single physicalchannel (e.g., metal wireline, an optical fiber, or a wireless channel,etc.). After reading this specification and the accompanying figures, itwill be clear to those skilled in the art how to make and useembodiments of the present invention in which N equals a value of otherthan 64.

[0025] Multichannel serializer 201 receives T parallel words, word₁through word_(T), wherein T is a positive integer greater than zero, onbuses 221-1 through 221-T, respectively, and a clock signal from atiming source (e.g., timing source 203, timing source 303, etc.).Multichannel serializer 201 outputs a serialized version of word₁through word_(T) to serial communications channels 211-1 through 211-N,respectively. In accordance with the illustrative embodiment, T=16.After reading this specification and the accompanying figures, it willbe clear to those skilled in the art how to make and use embodiments ofthe present invention in which T equals a value of other than 16.

[0026] In accordance with the illustrative embodiment of the presentinvention, each of words word₁ through word_(T) comprises W bits,wherein W is a positive integer greater than zero. In accordance withthe illustrative embodiment, W=32. After reading this specification andthe accompanying figures, it will be clear to those skilled in the arthow to make and use embodiments of the present invention in which Wequals a value of other than 32. Furthermore, after reading thisspecification and the accompanying figures, it will be clear to thoseskilled in the art how to make and use embodiments of the presentinvention in which some of word₁ through word_(T) comprise a differentnumber of bits than other of word₁ through word_(T) comprise.

[0027] When multichannel serializer 201 multiplexes two or more bitsfrom a single word over one serial communications channel, all of thebits from the word that are multiplexed over the same serialcommunications channel are called a “symbol.” In accordance with theillustrative embodiment of the present invention, each word of word₁through word_(T) comprises M symbols, wherein M is equal to N/T. Inaccordance with the illustrative embodiment, M=N/T=64/16=4. Afterreading this specification and the accompanying figures, it will beclear to those skilled in the art how to make and use embodiments of thepresent invention in which M equals a value of other than 4.Furthermore, after reading this specification and the accompanyingfigures, it will be clear to those skilled in the art how to make anduse embodiments of the present invention in which some of words word₁through word_(T) comprise a different number of symbols than other ofwords word₁ through word_(T).

[0028] In accordance with the illustrative embodiment, there are K=W/Mbits in each “unencoded” symbol before it is encoded with parity orframing bits or both parity and framing bits. In accordance with theillustrative embodiment, the number of bits in each unencoded symbolequals K=W/M=32/4=8.

[0029] In accordance with the illustrative embodiment, each unencodedsymbol is scrambled with a deterministically invertable function, Ψ( ),to increase the likelihood that any given bits is a “1” to 50%, whichincreases the transition density on the serial communications channeland increases the likelihood that symbol and frame alignment will beperformed correctly by the deserializer. The process of scramblingneither adds nor removes bits nor adds nor removes redundancy from theunencoded symbol. The process for scrambling is described in detailbelow.

[0030] Furthermore, each scrambled and unencoded symbol is encoded withparity bits for the purpose of forward error correction. The forwarderror correction technique employed by the illustrative embodiment isdescribed in detail below.

[0031] And still furthermore, and to facilitate symbol and wordsynchronization by deserializer 202, each scrambled and unencoded symbolis also encoded with framing bits. The framing technique employed by theillustrative embodiment is described in detail below.

[0032] In all cases, the number of bits transmitted with respect to eachsymbol is B=K+Z, wherein Z equals the number of bits added to the symbolas parity and framing bits.

[0033] In accordance with the illustrative embodiment, the bits in eachsymbol are encoded with 2 additional bits, and, therefore, Z=2 andB=K+Z=32/4+2=10. How these two additional bits are generated andtransmitted is described in detail below. After reading thisspecification and the accompanying figures, it will be clear to thoseskilled in the art how to make and use embodiments of the presentinvention in which the bits in each symbol are encoded with a differentnumber of additional bits.

[0034] In accordance with the illustrative embodiment, multichannelserializer 201 uses a binary modulation scheme (e.g., binaryshift-keying, etc.) and transmits each bit independently over a serialcommunications channel. In some alternative embodiments of the presentinvention however, multichannel serializer combines the bits from two ormore serial communications channels using a non-binary modulation scheme(e.g., quadriphase-shift keying, etc.) and transmits multiple bitssimultaneously over a serial communications channel.

[0035] Multichannel serializer 201 outputs N sets of B bits onto each ofserial communications channels 211-1 through 211-N for each set of Twords received by multichannel serializer 201. The details ofmultichannel serializer 201 are described below and with respect toFIGS. 4 through 8. Multichannel serializer 201 operates inpipeline-processor fashion, meaning that it continually receives one setof T parallel words after another and transmits N sets of B bits ontoeach of serial communications channels 211-1 through 211-N for each setof T words received by it.

[0036] In accordance with the illustrative embodiment, the propagationdelay through each of serial communications channels 211-1 through 211-Nneed not be the same nor need it remain constant throughout time.

[0037] Multichannel deserializer 202 receives a serialized stream ofbits from each of serial communications channels 211-1 through 211-N,and a clock signal (e.g., from timing source 204, from timing source303, etc.), and from them reconstructs and outputs T parallel words,word₁ through word_(T), on buses 222-1 through 222-T. Furthermore,multichannel deserializer 202 operates in pipeline-processor fashion,meaning that it continually outputs one set of T parallel words afteranother for each of the N sets of B bits it receives from serialcommunications channels 211-1 through 211-N.

[0038] Timing source 204/303 generates a plurality of differently-phasedtiming signals for multichannel serializer 201. To this end, timingsource 204/303 generates B timing signals, Φ₀ through Φ_(B), each withthe same frequency but 360°/B out of phase with respect to each other.The frequency of each of the timing signals equals the frequency withwhich words are loaded into multichannel serializer 201.

[0039] For example, in accordance with the illustrative embodiment, B=10and, therefore, timing source 204/303 generates ten (10) clock signalsdepicted in Table 1. TABLE 1 Clock signals From Timing Source 204/303(for B = 10) Clock Signal No. Phase Φ₀  0° Φ₁  36° Φ₂  72° Φ₃ 108° Φ₄144° Φ₅ 180° Φ₆ 216° Φ₇ 252° Φ₈ 288° Φ₉ 324°

[0040] It will be clear to those skilled in the art how to make and usetiming source 204/303.

[0041]FIG. 4 depicts a block diagram of the salient components ofmultichannel serializer 201, which comprises: T word modules 401-1though 401-T, N encoder/framers 402-1 through 402-N, N single channelserializers 403-1 through 403-N, and N modulators 404-1 through 404-N,interconnected as shown.

[0042] In accordance with the illustrative embodiment, multichannelserializer 201 is fabricated on an integrated circuit. For the purposesof this specification, the term “integrated circuit” is defined as aslice or chip of material on which is etched or imprinted a complex ofelectronic components and their interconnections.

[0043] Word module 401-f, for f=1 to T, receives a W-bit word from bus221-f divides the W-bit word into M K-bit unencoded symbols, anddistributes each of the K-bit unencoded symbols to one of theencoder/framers associated with word module 401-f. In the illustrativeembodiment, each word module receives 32 bits, divides the 32 bits intofour unencoded symbols of 8 bits each, and distributes each unencodedsymbol to one of the four encoder/framers associated with the wordmodule.

[0044] Encoder/framer 402-i, for i=1 to N, receives S consecutive groupsof K bits, b₀ through b_(K-1), in parallel and timing signal Φ₀ fromtiming source 204/303 and outputs an S by K+2 array of S(K+2) bits thatare represented by a two-dimensional matrix G, as described below, tosingle channel serializer 403-i. Encoder/framer 402-i is described indetail below and with respect to FIG. 5.

[0045] Single channel serializer 403-i receives the two-dimensionalmatrix G from encoder/framer 402-i and timing signal Φ₀ from timingsource 204/303 and serializes the matrix G onto serial communicationschannel 211-i. U.S. patent application Ser. No. 10/011,938, filed onDec. 5, 2001, and entitled “Serializer” is incorporated by reference andteaches one technique for making and using single channel serializer403-i.

[0046] Modulator 404-i receives the serialized bit stream from singlechannel serializer 403-i and modulates it, in well-known fashion, ontoserial communications channel 221-i.

[0047]FIG. 5 depicts a block diagram of the salient components ofencoder/framer 402-i, which comprises: frame pulse generator 501,scrambler 502, row parity generator 503, column parity generator 504,first-in-first-out memory (“FIFO”) 505, multiplexor 506, and inverter507, interconnected as shown.

[0048] In accordance with the illustrative embodiment, encoder/framer402-i operates on each set of S consecutive K-bit unencoded symbols as aunit or “frame,” wherein S is a positive integer greater than zero. Inparticular, every S sets of K-bit symbols are treated as an S by K arrayof SK bits that are represented by the two-dimensional matrix A.$\begin{matrix}{A = \begin{bmatrix}a_{0,0} & \cdots & a_{0,{S - 1}} \\\vdots & ⋰ & \vdots \\a_{{K - 1},0} & \cdots & a_{{K - 1},{S - 1}}\end{bmatrix}} & \left( {{Eq}.\quad 1} \right)\end{matrix}$

[0049] Encoder/framer 402-1 operates on S symbols as a unit because ofefficiencies and opportunities that arise when multiple symbols areoperated on together that are not possible or are less feasible or areless efficient when only individual symbols are considered.

[0050] In accordance with the illustrative embodiment, S=64. Afterreading this specification it will be clear to those skilled in the arthow to make and use embodiments of the present invention in which Sequals a value of other than 64.

[0051] To ensure that all of the components of encoder/decoder 402-itreat the same S symbols as one frame, frame pulse generator 501generates a “framing pulse” that delineates the end of one frame and thebeginning of the next. The framing pulse is generated once every Scycles of timing signal Φ₀ and is distributed to row parity generator503, column parity generator 504, and multiplexor 506.

[0052] In accordance with the illustrative embodiment, scrambler 501performs a deterministically invertable function, Ψ( ), on A (i.e., Ψ( )is deterministically invertible if and only if C=Ψ(A) and A=Ψ′(C)), inwell-known fashion. The output of scrambler 501 can be conceptualized asan S by K array of SK bits that are represented by the two-dimensionalmatrix C, wherein:

C=Ψ(A)  (Eq. 2)

[0053] and: $\begin{matrix}{C = \begin{bmatrix}c_{0,0} & \cdots & a_{0,{S - 1}} \\\vdots & ⋰ & \vdots \\c_{{K - 1},0} & \cdots & c_{{K - 1},{S - 1}}\end{bmatrix}} & \left( {{Eq}.\quad 3} \right)\end{matrix}$

[0054] Matrix C is transmitted to row parity generator 503, columnparity generator 504, and FIFO 505 K-bits at a time via a K-bit widebus.

[0055] In accordance with the illustrative embodiment, yK “row” paritybits and S/y “column” parity bits are generated based on C, wherein yKand S/y are positive integers greater than zero. In accordance with theillustrative embodiment, y=2. In some alternative embodiments of thepresent invention, y equals a value other than 2 (e.g., ½, ⅓, ¼, 3, 4,etc.) and after reading this specification it will be clear to thoseskilled in the art how to make and use embodiments of the presentinvention in which y equals a value other than 2.

[0056] The row parity bits and column parity bits enable multichanneldeserializer 202 to correct and/or detect some bit errors in C thatresult during the transmission of C from multichannel serializer 201 tomultichannel deserializer 202.

[0057] In accordance with the illustrative embodiment, row paritygenerator 503 generates yK “row” parity bits, RP_(p), for p=0 to yK−1,such that: $\begin{matrix}{{RP}_{p} = \left\{ \begin{matrix}{{\left( {\sum\limits_{i = 0}^{\frac{S}{y}1}c_{p,i}} \right){mod}\quad 2\quad {for}\quad p} = {{0\quad {to}\quad K} - 1}} \\{{\left( {\underset{i = \frac{S}{y}}{\sum\limits^{S - 1}}c_{p,i}} \right){mod}\quad 2\quad {for}\quad p} = {{K\quad {to}\quad {yK}} - 1}}\end{matrix} \right.} & \left( \text{Eq.~~4a} \right)\end{matrix}$

[0058] The yK row parity bits are output from row parity generator 503to multiplexor 506 via a yK width bus after the conclusion of thereceipt of C by row parity generator 503. After reading thisspecification, it will be clear to those skilled in the art how totransmit the yK row parity bits from row parity generator 503 tomultiplexor 506 serially or via a different width bus.

[0059] In accordance with the illustrative embodiment, column paritygenerator 504 generates S/y “column” parity bits, CP_(q), for q=0 toS/y−1, such that: $\begin{matrix}{{CP}_{q} = {\left( {\sum\limits_{j = 0}^{K - 1}\left( {c_{j,q} + c_{{j + K},q}} \right)} \right){mod}\quad 2}} & \text{(Eq.~~5a)}\end{matrix}$

[0060] The S/y column parity bits are output from column paritygenerator 504 to multiplexor 506 serially after the conclusion of thereceipt of C by column parity generator 504. After reading thisspecification, it will be clear to those skilled in the art how totransmit the S/y column parity bits from row parity generator 503 tomultiplexor 506 via a bus.

[0061] The parity bits RP_(p) and CP_(q) are called “row” and “column”parity bits, respectively, not because they are based on the rows andcolumns of C, but rather because they are based on the rows and columnsof a matrix D that is based on a “shuffling” function, Λ( ), of C. Inparticular:

D=Λ(C)  (Eq. 6)

[0062] and $\begin{matrix}{D = {\begin{bmatrix}c_{0,0} & \cdots & c_{0,{\frac{S}{2} - 1}} \\\vdots & ⋰ & \vdots \\c_{{K - 1},0} & \cdots & c_{{K - 1},{\frac{S}{2} - 1}} \\c_{0,\frac{S}{2}} & \cdots & c_{0,{S - 1}} \\\vdots & ⋰ & \vdots \\c_{{K - 1},\frac{S}{2}} & \cdots & c_{{K - 1},{S - 1}}\end{bmatrix} = \begin{bmatrix}d_{0,0} & \ldots & d_{0,{\frac{S}{2} - 1}} \\\vdots & ⋰ & \vdots \\d_{{{2K} - 1},0} & \cdots & d_{{{2K} - 1},{\frac{S}{2} - 1}}\end{bmatrix}}} & \left( {{Eq}.\quad 4} \right)\end{matrix}$

[0063] The number of row and column parity bits needed for a matrix isequal to one-half of the perimeter of the matrix (i.e., one bit for eachcolumn and each row of the matrix). In particular, when the row andcolumn parity bits are based on the rows and columns, respectively, ofthe matrix C, the total number of row and column parity bits is S+K(i.e., one bit for each column and each row of matrix C). In contrast,when the row and column parity bits are based on the rows and columns,respectively, of the matrix D, the total number of row and column paritybits is S/y+yK (i.e., one bit for each column and each row of matrix D).In summary, a more “square” matrix requires fewer row and column paritybits than a less “square” matrix. For the purposes of thisspecification, matrix D is defined to be more “square” than matrix Cwhen (S/y+yK)<(S+K). And because matrix D is merely a shuffled versionof matrix D, the information contained in matrix D is equivalent to theinformation contained in matrix C.

[0064] For the purposes of this specification, a “shuffling function” ofa matrix is defined as the transposition of an S by K matrix into an S/yby yK matrix, wherein S, K, yK and S/y are all positive integers greaterthan zero, and y is a positive number other than one (1). The fewestnumber of row and column bits are needed when the sum of S/y+yK isminimized.

[0065] For example, the S=64 by K=8 matrix C can be shuffled into manyforms as shown in Table 2. As can be seen in Table 2, the fewest numberof row and column bits are needed when y=2 and y=4, and in accordancewith the illustrative embodiment, y=2. TABLE 2 Candidate Dimensions forMatrix D y S/y yK S/y + yK 64 1 512 513 32 2 256 258 16 4 128 132 8 8 6472 4 16 32 48 2 32 16 48 ½ 128 4 132 ¼ 256 2 258 ⅛ 512 1 513

[0066] In terms of matrix D, the row parity bits are based on the evenparity of each row of matrix D. In particular, row parity bit, RP_(p),for p=0 to yK−1, equals: $\begin{matrix}{{RP}_{p} = {\left( {\sum\limits_{i = 0}^{\frac{S}{2} - 1}d_{p,i}} \right){mod}\quad 2}} & \left( \text{Eq.~~~4b} \right)\end{matrix}$

[0067] In terms of matrix D, the column parity bits are based on theeven parity of each column of matrix D. In particular, column parity bitCP_(q), for q=0 to S/y−1, equals: $\begin{matrix}{{CP}_{q} = {\left( {\sum\limits_{j = 0}^{{2\quad K} - 1}d_{j,q}} \right){mod}\quad 2}} & \left( \text{Eq.~~~5b} \right)\end{matrix}$

[0068] After reading this specification, it will be clear to thoseskilled in the art how to make and use embodiments of the presentinvention that use other shuffling functions. Furthermore, after readingthis specification, it will be clear to those skilled in the art how tomake and use embodiments of the present invention that use odd parityfor the row parity bits or the column parity bits or both the row paritybits and the column parity bits. And still furthermore, after readingthis specification, it will be clear to those skilled in the art how tomake and use embodiments of the present invention in which matrix D isalso based on a transposition of matrix C.

[0069] In addition to the row parity bits and the column parity bits,encoder/framer 402-i also generates and transmits framing bits, whichfacilitate frame synchronization by multichannel deserializer 202. Inparticular, the illustrative embodiment advantageously generates Hframing bits, F₀ through F_(H-1), where H equals: $\begin{matrix}{H = {S - {yK} - \frac{S}{y}}} & \left( {{Eq}.\quad 7} \right)\end{matrix}$

[0070] In accordance with the illustrative embodiment, S=64, K=8, andy=2, and, therefore, H=64−16−32=16. In accordance with the illustrativeembodiment, F₀=1 and F₁ through F_(H-1) equal 0. After reading thisspecification, it will be clear to those skilled in the art how to makeand use embodiments of the present invention in which the framing bits,F₀ through F_(H-1), have a different value. Another reason for computingthe row and column parity bits based on matrix D, rather than on matrixC, is to free up bits to be used for framing.

[0071] Multiplexor 506 receives the yK row parity bits, the S/y columnparity bits and the H framing bits and from them constructs an S-bitvector, R₀ through R_(S-1). In particular: $\begin{matrix}{R = {\left\lbrack {R_{0}\quad \cdots \quad R_{S - 1}} \right\rbrack = \left\lbrack {F_{0}\quad \cdots \quad F_{H - 1}\quad {RP}_{0}\quad \cdots \quad {RP}_{{2K} - 1}\quad {CP}_{0}\quad \cdots \quad {CP}_{\frac{S}{2} - 1}} \right\rbrack}} & \left( {{Eq}.\quad 8} \right)\end{matrix}$

[0072] After reading this specification, it will be clear to thoseskilled in the art how to make and use embodiments of the presentinvention in which the vector R′ is any transposition of that shown inEquation 8. For example: $\begin{matrix}{R^{\prime} = \left\lbrack {F_{0}\quad {CP}_{0}\quad {RP}_{0}\quad {CP}_{1}\quad F_{1}\quad {CP}_{2}\quad {RP}_{1}\quad {CP}_{3\quad}F_{2}\quad \cdots \quad F_{K - 1}\quad {CP}_{\frac{S}{2} - 2}\quad {RP}_{K - 1}{CP}_{\frac{S}{2} - 1}} \right\rbrack} & \text{(Eq.~~~8b)}\end{matrix}$

[0073] FIFO 505 holds matrix C until multiplexor 506 is ready to outputthe vector R associated with matrix C, in well-known fashion.

[0074] Multiplexor 506 outputs the vector R directly to serializer 403-iand through inverter 507 to serializer 403-i, which creates an invertedcopy of vector R, {overscore (R)}, so that, overall, the output ofencoder/framer 402-i is an S by K+2 array of S(K+2) bits that arerepresented by the two-dimensional matrix G, wherein: $\begin{matrix}{G = \begin{bmatrix}\overset{\_}{R_{0}} & \cdots & \overset{\_}{R_{S - 1}} \\R_{0} & \cdots & R_{S - 1} \\c_{0,0} & \cdots & c_{0,{S - 1}} \\\vdots & ⋰ & \vdots \\c_{{K - 1},0} & \cdots & c_{{K - 1},{S - 1}}\end{bmatrix}} & \left( {{Eq}.\quad 9} \right)\end{matrix}$

[0075] An inverted copy of the vector R, {overscore (R)}, is generatedby encoder/framer 402-i and transmitted as part of the matrix G tofacilitate symbol synchronization by multichannel deserializer 202. Theadvantage of transmitting both the vector R and an inverted copy of thevector R, {overscore (R)}, is that the redundancy created by the pair ofvectors enables multichannel deserializer 202 to easily discern whichrows are which in matrix G. After reading this specification, it will beclear to those skilled in the art how to make and use embodiments of thepresent invention in which the rows or columns or rows and columns ofmatrix G are transposed.

[0076] Serializer 403-i transforms the two-dimensional matrix G into avector, X, for transmission via serial communications channel 211-i,wherein X equals:

X=[{overscore (R₀)} R₀ c_(0,0) . . . c_(K-1,0) . . . {overscore(R_(S-1))} R_(S-1) c_(0,S-1) . . . c_(K-1,S-1)]  (Eq. 10)

[0077] After reading this specification, it will be clear to thoseskilled in the art how to make and use embodiments of the presentinvention in which the items in vector X are transposed.

[0078]FIG. 6 depicts a block diagram of the salient components ofmultichannel deserializer 202, which comprises: N demodulators 601-1through 601-N, N single-channel deserializers 602-1 through 602-N, Ndecoder/deframers 603-1 through 603-N, and T word synchronizationmodules 604-1 through 604-T, interconnected as shown.

[0079] Demodulator 601-i, for i=1 to N, receives a modulated signal fromserial communications channel 212-i, demodulates the modulated signal,and outputs a serialized stream of bits to single channel deserializer602-1. It is well known to those skilled in the art how to make and usedemodulator 601-i.

[0080] Single-channel deserializer 602-i, for i=1 to N, receives: (1)the serialized stream of bits from demodulator 401-i and (2) the clocksignal from timing source 204/303 and outputs each group of B bits inparallel to decoder/deframer 603-i. It is well known to those skilled inthe art how to make and use single-channel deserializer 602-i. U.S.patent application Ser. No. 09/909,499, entitled “Deserializer,” whichis incorporated by reference, teaches one technique for making and usingsingle-channel deserializer 602-i.

[0081] Decoder/deframer 603-i receives groups of B bits in parallel fromsingle-channel deserializer 602-i. More often than not, the B bits in agroup include parts of two encoded symbols, and, therefore,decoder/deframer 603-i must re-group the bits so that each group of Bbits includes all of, and only parts of, one symbol. Furthermore,decoder/deframer 603-i also generates a frame synchronization pulse toenable the delineation of adjacent frames, and performs forward errorcorrection on the bits in the decoded K-bit symbols. The details ofdecoder/deframer 603-i are described in detail below and with respect toFIG. 7.

[0082] Word synchronization module 604-f receives M K-bit symbols andframe synchronization pulses from its M associated decoder/deframers andresynchronizes the words (i.e., regroups the symbols into words) inwell-known fashion. It is well known to those skilled in the art how tomake and use word synchronization module 604-f. The output of wordsynchronization module 604-f is word f on bus 222-f.

[0083]FIG. 7 depicts a block diagram of the salient components ofdecoder/deframer 603-i, which comprises: symbol resynchronizer 701,frame pulse generator 702, demultiplexor 703, first-in first-out memory(“FIFO”) 704, forward error corrector 705, descrambler 706, row paritygenerator 707, and column parity generator 708, interconnected as shown.

[0084] Symbol resynchronzer 701 receives groups of B bits in parallelfrom single channel deserializer 602-i and identifies which of thosebits are associated with matrix C and which are associated with vectorsR and {overscore (R)}. Symbol resynchronizer 701 identifies which bitsare associated with vectors R and {overscore (R)} by noting which pairsof bits are predominantly opposites of each other. The test is based on“predominance” rather than on “always” to account for possible bitserrors in R and {overscore (R)}.

[0085] When symbol resynchronizer 701 identifies which pairs of bits arepredominantly opposites of each other, and, thus represent the vectors Rand {overscore (R)}, symbol resynchronizer 701 forwards the bitsassociated with matrix C to FIFO 704 and forwards the bits associatedwith vector R to both frame pulse generator 702 and to demultiplexor703. The bits associated with the vector {overscore (R)} are discardedby symbol resynchronizer 701. In some alternative embodiments of thepresent invention, a comparison of the vectors R and {overscore (R)} cangive symbol resynchronizer 701 an indication of the bit error rate onserial communications channel 212-i.

[0086] Frame pulse generator 702 generates a pulse that is indicative ofthe boundaries between successive frames (i.e., successive instances ofthe matrix C) so that:

[0087] i. word synchronization module 604-f can properly align andreconstitute the K-bit symbols from different decoder/framers into theW-bit words from which they were derived, and

[0088] ii. demultiplexor 703 can distinguish between the row paritybits, the column parity bits and the framing bits from the succession ofbits it receives from symbol resynchronizer 701.

[0089] Frame pulse generator 702 identifies the boundaries betweensuccessive frames by scanning the succession of parity bits and framingbits received from symbol resynchronizer 701 for the pattern of framingbits, F₀ through F_(H-1), that were inserted into vector R bymultiplexor 506. Because the parity bits are based on the parity of ascrambled matrix, the likelihood that frame pulse generator 702 willmistake a pattern of parity bits for a pattern of framing bits isinversely related to the magnitude of H, as determined by Equation 7,the nature of the pattern of the framing bits, F₀ through F_(H-1), andthe occurrence of 1's and 0's in matrix C.

[0090] Demultiplexor 703 performs the inverse function of multiplexor506 in FIG. 5 and segregates the row parity bits, the column parity bitsand the framing bits from the succession of bits received from symbolresynchronizer 701. Demultiplexor 703 identifies the row parity bits,the column parity bits and the framing bits from each other based on:

[0091] i. the pattern used by multiplexor 506 for combining the rowparity bits, the column parity bits and the framing bits, and

[0092] ii. their phase alignment with respect to the framing pulsereceived from frame pulse generator 702.

[0093] Demultiplexor 703 discards the framing bits and transmits the yKrow parity bits and the S/y column parity bits to forward errorcorrector 705 via a yK+S/y bit bus.

[0094] FIFO 704 receives the S K-bit decoded symbols from symbolresynchronizer 701 and holds them until demultiplexor 703 has output theyK row parity bits and the S/y column parity bits to forward errorcorrector 705.

[0095] Forward error corrector 705 groups S K-bit symbols as a singleframe, matrix Ĉ, which is an estimate of matrix C before forward errorcorrection, based on the occurrence of the framing pulses from framepulse generator 702 and corrects some or all of the bit errors thatmight have occurred in the transmission of the S K-bit decoded symbols.The output of forward error corrector 705 is the matrix C and is fedinto descrambler 706. The details of forward error corrector 705 aredescribed in detail below and with respect to FIG. 8.

[0096] Descrambler 706 performs the inverse function of scrambler 501 torecover the matrix A. In particular, descrambler 706 performs:

A=Ψ′(C)  (Eq. 11)

[0097] in well-known fashion. The output of descrambler 706, matrix A,is output to word synchronization module 604-f via a K-bit bus.

[0098] Row parity generator 707 is identical to row parity generator 503in FIG. 5 and generates yK candidate row parity bits, {circumflex over(R)}P_(p), for p=0 to yK−1, which will be compared with row parity bitsfrom demultiplexor 703 to determine if a bit error has occurred in therow associated with the respective parity bits.

[0099] Similarly, column parity generator 707 is identical to columnparity generator 504 in FIG. 5 and generates S/y candidate column paritybits, ĈP_(q), for q=0 to S/y−1, which will be compared with the columnparity bits from demultiplexor 703 to determine if a bit error hasoccurred in the column associated with the respective parity bits.

[0100]FIG. 8 depicts a block diagram of the salient components offorward error corrector 705, which comprises: row parity bit decoder801, column parity bit decoder 802, Boolean AND gates 803-0 though803-(K−1), and Boolean Exclusive-OR gates 804-0 through 804-(K−1),interconnected as shown.

[0101] The estimate of matrix C, Ĉ, is input into forward errorcorrector 705 one column at a time (i.e., K-bits at a time) with bitĉ_(vj) on lead 811-v, for v=0 to K−1 and j=0 to S−1. Forward errorcorrector 705 corrects, if necessary, the bits in Ĉ one column at a timeto produce the matrix C with bit c_(vj) on lead 813-v, for v=1 to K−1and j=0 to S−1. The criteria for correcting the bits in Ĉ is describedbelow.

[0102] Row parity bit detector 801 receives the yK row parity bits,RP_(p), from demultiplexor 703 and the yK row parity bits, {circumflexover (R)}P_(p), from row parity generator 707, and compares thembit-wise to determine if a bit error has occurred in a row of matrix D.In particular, row parity bit detector 801 computes an error term,ER_(p), which is equal to:

ER_(p)=RP_(p)⊕{circumflex over (R)}P_(p)  (Eq. 12)

[0103] and outputs the value of ER_(v) to Boolean AND gate 803-v for j=0to S/y−1 and ER_(v+K) to Boolean AND gate 803-v for j=S/y to S−1.

[0104] Similarly, column parity bit decoder 802 receives the S/y columnparity bits, CP_(q), from demultiplexor 703 and the S/y column paritybits, ĈP_(q), from column parity generator 708, and compares thembit-wise to determine if a bit error has occurred in a column of matrixD. In particular, column parity bit detector 802 computes an error term,EC_(q), which is equal to:

EC_(q)=RC_(q)⊕{circumflex over (R)}C_(q)  (Eq. 13)

[0105] and outputs the value of EC_(j mod y) onto lead 814.

[0106] The net effect of forward error detector 705 is to invert anestimate of a bit in matrix Ĉ when and only when both the row parity andthe column parity for that bit indicate that an error has occurred. Inother words, forward error detector 705 inverts the received a bit in Ĉ,as designated by {circumflex over (d)}_(i,j) in matrix {circumflex over(D)} when and only when ER_(i) and EC_(j) indicate an error, wherein:

{circumflex over (D)}=Λ(Ĉ)  (Eq. 14)

[0107] and $\begin{matrix}{\hat{D} = {\begin{bmatrix}{\hat{c}}_{0,0} & \cdots & {\hat{c}}_{0,{\frac{S}{2} - 1}} \\\vdots & ⋰ & \vdots \\{\hat{c}}_{{K - 1},0} & \cdots & {\hat{c}}_{{K - 1},{\frac{S}{2} - 1}} \\{\hat{c}}_{0,\frac{S}{2}} & \cdots & {\hat{c}}_{0,{S - 1}} \\\vdots & ⋰ & \vdots \\{\hat{c}}_{{K - 1},\frac{S}{2}} & \cdots & {\hat{c}}_{{K - 1},{S - 1}}\end{bmatrix} = \begin{bmatrix}{\hat{d}}_{0,0} & \ldots & {\hat{d}}_{0,{\frac{S}{2} - 1}} \\\vdots & ⋰ & \vdots \\{\hat{d}}_{{{2K} - 1},0} & \cdots & {\hat{d}}_{{{2K} - 1},{\frac{S}{2} - 1}}\end{bmatrix}}} & \left( {{Eq}.\quad 15} \right)\end{matrix}$

[0108] It is to be understood that the above-described embodiments aremerely illustrative of the present invention and that many variations ofthe above-described embodiments can be devised by those skilled in theart without departing from the scope of the invention. It is thereforeintended that such variations be included within the scope of thefollowing claims and their equivalents.

What is claimed is:
 1. A method comprising: receiving a matrix C ofbits, wherein said matrix C has dimensions of S by K and wherein both Sand K are positive integers; generating a plurality of row parity bitsthat are indicative of the parity of a row of bits in a matrix D thathas dimensions of S/y by yK, wherein S/y and yK are positive integers,wherein y is a positive integer other than one, and wherein matrix D isbased on a shuffling function of matrix C; and transmitting said matrixC of bits and said plurality of row parity bits.
 2. The method of claim1 wherein S/y+yK<S+K.
 3. The method of claim 1 further comprising:generating a plurality of column parity bits that are indicative of theparity of a column of bits in matrix D; and transmitting said matrix Cof bits, said plurality of row parity bits, and said plurality of columnparity bits.